The invention relates to a method for producing cavities (air gaps), which are patterned in submicrometer dimensions, in an cavity layer of a semiconductor device using a freezing process liquid, and to a configuration which is fabricated by the method and has cavities, which have been patterned in submicrometer dimensions, in a semiconductor device.
Within a semiconductor device, interconnects are capacitively coupled to one another both within an interconnect layer (intralevel) and between different interconnect layers (interlevel). Capacitive coupling between interconnects of this nature leads to crosstalk and lengthened signal propagation times.
To minimize the disruptive effects, the interconnects are decoupled from one another as best they can be by keeping the capacitance between them at as low a level as possible. For a given spacing between two interconnects, this requires the material between the interconnects to have the lowest possible permittivity. Gaseous substances, i.e. air, have a virtually optimal permittivity of almost 1 at standard pressure, while the permittivity of solids is generally much higher.
Therefore, it is generally attempted in semiconductor devices to capacitively decouple the interconnects from one another by use of air-filled cavities. The text that follows will describe the known methods for producing cavities of this type. All the methods are based on a process layer that has already been patterned by ribs and trenches.
In functional terms, the ribs of the process layer may be interconnects. The trenches in the process layer are as yet uncovered cavities. Accordingly, an interconnect layer is one possible (but not the only) embodiment of a cavity layer which results from the process layer.
According to a first method, the trenches are filled with porous materials, such as xerogels or aerogels, and are then covered with a covering layer made from a dielectric. The air which is enclosed in the pores reduces the overall permittivity of the material between the interconnects. Porous materials of this type are currently in the evaluation phase. Drawbacks of the method are the water uptake on account of the capillary effect in open-pored structures, and the relatively long process times. Furthermore, filling the cavities with xerogel and aerogel material increases the permittivity of the air gaps compared to a pure air filling. The use of aerogels as dielectrics with a low permittivity is described, for example, in the reference titled xe2x80x9cThe Effect Of Sol Viscosity On The Sol-Gel Derived Low-Density SiO2 Xerogel Film For Intermetal Dielectric Applicationxe2x80x9d, Thin Solid Films, vol. 332, p. 449-454, 1998.
A second method is for trenches to be covered by conventional SiO2 chemical vapor deposition (CVD) processes with a high deposition rate.
A first variant of a method of this type is described in the reference by B. P. Shieh, et al., titled xe2x80x9cAir-Gap Formation During IMD Deposition to Lower Interconnect Capacitancexe2x80x9d, IEEE Electron Device Letters, Vol. 19, No. 1, pp. 16-18, January 1998. However, cavities produced in this way extend into the covering SiO2 layer (formation of small hats). During subsequent chemical mechanical polishing (CMP) processes, the cavities below can be opened up, and adjacent interconnects can be short-circuited by subsequent metallization in the opened cavities. If the SiO2 layer is deposited in a size that is such that it rules out subsequent opening of the cavities, the problem is then of making contact with interconnects below it through sufficiently deep vias.
In a variant of this method, described in the reference by T. Ueda, et al., titled xe2x80x9cA Novel Air Gap Integration Scheme for Multi-level Interconnects using Self Aligned Via Plugsxe2x80x9d, Symp. on VLSI Technology, pp. 46, 47, June 1998, the trenches are covered using a two-stage process. In a first stage, SiO2 is deposited on the horizontal surfaces of the ribs using a plasma enhanced chemical vapor deposition (PECVD) process. Narrow trenches are covered by the SiO2 that grows on the surfaces of the ribs on both sides of the trenches. In a subsequent high-density plasma CVD process, wider trenches are filled with SiO2 and narrow trenches are sealed with SiO2.
According to a third method, described in the reference by J. G. Fleming, E. Roherty-Osmum, titled xe2x80x9cUse of Air-Gap Structures to Lower Intralevel Capacitacexe2x80x9d, Proc. DUMIC, pp. 139-145, 1997, spin-on materials are used to cover the cavities between the interconnects. The drawback of the method is the subsequent flow of the materials into the cavities.
A fourth method is described in International Patent Disclosure WO 97/39484 A1 (Rosenmayer, Noddin). In this method, a film is placed onto the interconnect layer, which has been patterned by trenches and ribs. A film of this type is at least a few micrometers thick, so that it can be reliably processed. Therefore, as above, there are considerable distances between the interconnect levels, with the drawbacks described of making contact using vias.
A fifth method, which is described in U.S. Pat. No. 6,165,890 (Kohl et al.), is the retropolymerization of polynorbornene, which temporarily fills the cavities between the interconnects. In this method, inevitable residues of the retropolymerization may lead to clusters that are critical with regard to short circuits. Furthermore, the choice of a dielectric between the interconnect layers is limited, since the material has to be permeable to the volatile substances which form during the retropolymerization.
Similar drawbacks result from a sixth method, the thermal decomposition of a temporary filling of the cavities between the interconnects. An example of thermal decomposition of a temporary filling with a photoresist is described in U.S. Pat. No. 5,668,398 (Havemann et al.). The oxidation of a temporary carbon layer forms the subject of a reference by M. B. Anand, M. Yamada, H. Shibata, titled xe2x80x9cNURA: A Feasible, Gas Dielectric Interconnect Processxe2x80x9d, Symp. on VLSI Technology, pp. 82, 83, June 1996. In both cases, the substances formed during the decomposition have to be forced through the covering layer, which restricts the choice of materials. The residues in the cavities that cannot be decomposed increase the permittivity and/or reduce the protection against short circuits. According to a further example, which is known from International Patent Disclosure WO 00/51177 (Werner, Pellerin), for the decomposition of a temporary filling, the covering layer is perforated before the decomposition of the filling, in order to accelerate or improve the expulsion of the decomposition residues.
According to a seventh method, which is known from U.S. Pat. No. 5,599,745 (Reinberg), a dielectric is applied to the ribs formed by the interconnects, is partially melted until this layer bulges out over the interconnect. The bulges in the covering layer of closely adjacent interconnects ultimately come into contact with one another, so that the trenches between them are spanned.
A description which summarizes known methods for producing cavities in a semiconductor substrate is described, together with an assessment of the results which can be achieved by these methods, in the article by Ben Shieh, Krishna Saraswat, Mike Deal, Jim McVittie, titled xe2x80x9cCavities Lower k Of Interconnect Dielectricsxe2x80x9d Solid State Technology, February 1999.
To summarize, the drawbacks of the methods which have been described are:
a) residues in the cavities, which increase the permittivity and/or reduce the protection against short circuits;
b) the thickness required of the layer which covers the trenches, and the difficulty of producing vias which such a thickness implies; and
c) process integration.
Furthermore, freezing sublimation techniques are known from the fabrication of open trench structures in semiconductor components that have microstructures. In these techniques, after a purging operation semiconductor devices are dried by the purge liquid that is still on the semiconductor device initially being frozen and then sublimed in the frozen state. This method prevents deformation and/or sticking of predominantly unsupported microstructures.
A t-butylalcohol freezing-sublimation method is described in the reference by Takeshima, N., et al., titled xe2x80x9cElectrostatic Parallelogram Actuatorsxe2x80x9d, in: 1991 International Conference on Solid-State Sensors and Actuators: Transducers 91, San Francisco, Calif., USA, 1991, pp. 63-66.
A critical transition from a liquid phase to a gas phase is avoided in the reference by Gregory T. Mulhern et al., titled xe2x80x9cSupercritical Carbon Dioxide Drying of Microstructuresxe2x80x9d in: Technical Digest of Transducers 93, 1993, pp. 296-298 as a result of the purge liquid being replaced by liquid carbon dioxide which is subsequently converted into a supercritical phase.
A further freezing-sublimation technique is described in International Patent Disclosure WO 90/09677 (Guckel, Sniegowski). The sublimation of the purge liquid from the solid phase prevents any deviation in any micromechanical structures on a semiconductor device during the drying operation.
It is accordingly an object of the invention to provide a method for producing cavities with submicrometer patterns in a semiconductor device by use of a freezing process liquid that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, which allows patterned cavities of submicrometer dimensions to be created in a cavity layer of a semiconductor device using methods and tools which are customary in semiconductor process engineering. The cavities are to be free of residues.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing patterned cavities having submicrometer dimensions in a cavity layer of a semiconductor device. The method includes providing a base layer, and applying a process layer to the base layer. The process layer initially is a compact, homogeneous process layer. The process layer is patterned for forming ribs having submicrometer dimensions and trenches between the ribs, the ribs being formed from layer material. The trenches are filled with a process liquid and the process liquid is then cooled to a temperature below its freezing point resulting in a frozen process liquid. A resulting process surface has sections formed from uncovered surfaces of the ribs and from a surface of the frozen process liquid. A covering layer is applied to the process surface resulting in the formation of cavities in areas where the covering layer covers the trenches. Finally, the process liquid is expelled from the cavities, thus completing a formation of the cavity layer from the process layer.
In the method according to the invention, therefore, the initially compact process layer is applied to the base layer and then patterned. In the process, ribs of submicrometer dimensions and trenches between the ribs are formed from the material of the process layer. The trenches are filled with a process liquid, and then the process liquid is cooled to a temperature below its freezing point. Then, a first covering layer is applied to a process surface that is composed of the surfaces of the process liquid that has been frozen in the trenches and the ribs. A cavity or air-gap layer is formed from the process layer as a result of the process liquid being expelled from the cavities formed by covering the trenches.
With a dielectric as the material used for the ribs, an cavity layer of this type can be used as an interlayer of low permittivity between two interconnect layers.
Preferably, however, the ribs are formed from a conductive material and in functional terms are interconnects. In this case, the cavity layer functions as an interconnect layer (also referred to below as a metallization level). The metallization level is applied using a conventional technique according to one of the two following processes.
According to a first process, an auxiliary layer, which is formed of an auxiliary material, is deposited on the base layer. A photoresist is applied to the auxiliary layer and is patterned by a lithographic process. In the process, the auxiliary layer is uncovered in sections. The uncovered sections of the auxiliary layer are removed, leading to the formation of auxiliary trenches in the auxiliary layer. Then, a layer of a conductive material is applied over the entire surface, the auxiliary trenches being filled with the conductive material. Then, the conductive material is ground away again until the original surface of the auxiliary layer is reached. The auxiliary material is etched out of a process layer that has been formed in this way and has been patterned by the conductive material and the auxiliary material, using an etching medium, so that only ribs of the conductive material remain. This technique is also known as the Damascene technique.
According to a second method, a compact, homogeneous layer of the conductive material forms the process layer. A lithographic process is used to pattern a photoresist on the process layer. The process layer is etched according to the pattern of the photoresist. Ribs containing the conductive material of submicrometer dimensions and trenches that lie between the ribs are formed.
The base layer is preferably formed as an etching stop layer, in order to allow or simplify the patterning of the process layer.
If the cavity layer which has been developed from the process layer is to be formed as an interconnect layer, the material used for the ribs of the process layer is a conductive material, preferably copper.
If the purpose of the cavity layer is capacitive decoupling of two interconnect layers, the material used for the ribs is preferably a dielectric of low permittivity.
The trenches in the process layer preferably extend as far as the base layer, in order to achieve the highest possible overall permittivity between adjacent ribs.
For the same reason, the trenches are also ideally filled with the process liquid all the way up to the top edge of the ribs.
Suitable process liquids are in particular liquids which can condense on the surface of the process layer at approximately standard pressure (i.e. 1.013*105) and temperature and the freezing points of which, at standard pressure, are close to standard temperature (i.e. 25xc2x0 C.), and which, furthermore, can easily be forced through a first covering layer which is subsequently applied.
It is particularly preferable for 1,3-propanediol to be used as process liquid.
Further suitable liquids are alcohols, such as cyclohexanol, and also acetophenone and water.
Partial etching of the surfaces of the ribs improves the adhesion of the first covering layer that has been applied to the surfaces. The partial etching preferably takes place in a hydrogen plasma.
In a preferred variant of the method according to the invention, the first covering layer contains a layer of amorphous hydrocarbon with a submicrometer thickness and is deposited using a CVD process. The deposition operation is stopped as soon as the deposited layer is thick enough to span the trenches without support.
The CVD process is preferably a PECVD process using the process gases ethene and thiophene.
The process liquid is forced through the first covering layer by being heated. Polymerization of the first covering layer and expulsion of the process liquid may preferably take place in the same process step, for example by slow heating to approximately 200xc2x0 C.
As the process continues, a second covering layer made from a dielectric of low permittivity can be applied to the first covering layer, which is typically only 60 nanometers thick. The dielectric is preferably an organic dielectric, for example polybenzoxazole or an a-C:F(H) film. In the text which follows, contact holes can be etched into the double layer containing the first covering layer of amorphous hydrocarbon and the second covering layer containing an organic dielectric in a similar way within one process step.
However, silicon dioxide is also suitable as a material for a second covering layer.
The method according to the invention produces a semiconductor device that, in the cavity layer, has virtually ideal cavities. The low permittivity of the cavities optimally decouples interconnects which are separated by the cavities.
Therefore, the invention also relates to a configuration in a semiconductor device, containing a base layer, a cavity layer that is positioned on the base layer and has a pattern of submicrometer dimensions. The cavity layer contains ribs made from a layer material and cavities. A first covering layer formed of a polymer, rests on the ribs and covers the cavities.
The first covering layer preferably has a thickness of less than 100 nanometers.
The base layer is preferably an etching stop layer, and formed of silicon nitride.
In a preferred variant of the configuration according to the invention, the ribs formed of a layer material contain a conductive material and, particularly preferably, of copper.
A second covering layer, which rests on the first covering layer containing the polymer, may be added to the configuration.
The second covering layer preferably is formed of an organic dielectric.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing cavities with submicrometer patterns in a semiconductor device by use of a freezing process liquid, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.